US 12,323,151 B2
System and semiconductor device therein
Tsung-Che Lu, Tainan (TW); Chin-Ming Fu, Hsinchu County (TW); and Chih-Hsien Chang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 11, 2024, as Appl. No. 18/409,948.
Application 18/409,948 is a continuation of application No. 17/828,834, filed on May 31, 2022, granted, now 11,909,399.
Prior Publication US 2024/0146288 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/01 (2006.01); G06F 1/06 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/01 (2013.01) [G06F 1/06 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a measuring device configured to measure a voltage difference; and
a signal generating device configured to adjust the voltage difference according to a first enable signal, configured to divide a first clock signal to generate a second enable signal, and configured to delay the second enable signal to generate the first enable signal,
wherein the signal generating device comprises a first flip flop,
a data input terminal of the first flip flop is configured to receive the first clock signal, and
a clock input terminal of the first flip flop is configured to receive the first enable signal.