US 12,323,145 B2
Method and system for reconfigurable parallel lookups using multiple shared memories
Anh T. Tran, Santa Clara, CA (US); Gerald Schmidt, San Jose, CA (US); Tsahi Daniel, Palo Alto, CA (US); and Saurabh Shrivastava, Saratoga, CA (US)
Assigned to MARVELL ASIA PTE, LTD., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Jul. 27, 2022, as Appl. No. 17/874,544.
Application 16/996,749 is a division of application No. 15/923,851, filed on Mar. 16, 2018, granted, now 10,782,907.
Application 15/446,297 is a division of application No. 14/142,511, filed on Dec. 27, 2013, granted, now 9,620,213.
Application 17/874,544 is a continuation of application No. 16/996,749, filed on Aug. 18, 2020, granted, now 11,435,925.
Application 15/923,851 is a continuation of application No. 15/446,297, filed on Mar. 1, 2017, granted, now 9,952,800.
Prior Publication US 2022/0404995 A1, Dec. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 15/04 (2006.01); H03K 19/17728 (2020.01); H04L 45/745 (2022.01); H04L 45/7452 (2022.01); G06F 12/0864 (2016.01); H04L 45/7453 (2022.01)
CPC H03K 19/17728 (2013.01) [G06F 3/061 (2013.01); G06F 3/0644 (2013.01); G06F 3/0683 (2013.01); G11C 15/04 (2013.01); H04L 45/745 (2013.01); H04L 45/7452 (2022.05); G06F 12/0864 (2013.01); H04L 45/7453 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A tile device comprising:
M memories that each have a unique memory identifier (Mem ID), wherein each of the M memories include 2m entries, wherein each of the entries contains P pairs, each of the P pairs comprising a pre-programmed key and pre-programmed data; and
a matching and selection logic configured to receive an input key and output a lookup result, where M is a positive integer value greater than 1, and m and P are positive integer values.