US 12,323,142 B2
Integrated power management cells for gate all around technologies
Ramaprasath Vilangudipitchai, San Diego, CA (US); Venkat Narayanan, San Diego, CA (US); Giby Samson, San Diego, CA (US); and Venugopal Boynapalli, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 7, 2023, as Appl. No. 18/504,062.
Prior Publication US 2025/0150080 A1, May 8, 2025
Int. Cl. H03K 3/012 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/012 (2013.01); H03K 3/356113 (2013.01)] 19 Claims
OG exemplary drawing
 
1. At least one integrated power management cell of an integrated circuit (IC), comprising:
a first cell, the first cell being a 4-height cell, the first cell including a first row, a second row, a third row, and a fourth row,
the first cell comprising:
a first continuous n-type well (n-well) extending in a first direction across portions of the first row and the second row of the first cell to edges of the first cell;
a first power interconnect extending in the first direction along edges of both the first row and the second row of the first cell, the first power interconnect being coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well;
a second continuous n-well extending in the first direction across portions of the third row and the fourth row of the first cell to edges of the first cell;
a second power interconnect extending in the first direction along edges of both the third row and the fourth row of the first cell, the second power interconnect being coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well;
a first subset of a first voltage level shifter in one of the first row or the second row of the first cell, the first subset of the first voltage level shifter being associated with the first voltage domain and coupled to the first power interconnect; and
a second subset of the first voltage level shifter in one of the third row or the fourth row of the first cell, the second subset of the first voltage level shifter being associated with the second voltage domain and being coupled to the second power interconnect.