US 12,323,067 B2
Control systems and methods for turning off transistors associated with auxiliary windings and turning on transistors associated with primary windings
Qian Fang, Shanghai (CN); Yun Sun, Shanghai (CN); Penglin Yang, Shanghai (CN); and Yuan Lin, Shanghai (CN)
Assigned to On-Bright Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed by ON-BRIGHT ELECTRONICS (SHANGHAI) CO., LTD., Shanghai (CN)
Filed on Sep. 21, 2022, as Appl. No. 17/949,762.
Claims priority of application No. 202111166601.6 (CN), filed on Sep. 30, 2021.
Prior Publication US 2023/0099279 A1, Mar. 30, 2023
Int. Cl. H02M 3/335 (2006.01)
CPC H02M 3/33592 (2013.01) [H02M 3/33507 (2013.01); H02M 3/33515 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A system for controlling turning on a first transistor and turning off a second transistor, the system comprising:
a logic signal generator configured to:
process information associated with a first voltage related to a second voltage of a first auxiliary winding, the first auxiliary winding being coupled to a primary winding, a secondary winding, and a second auxiliary winding;
generate a third voltage based on at least information associated with the first voltage, the third voltage indicating a first voltage difference from a drain terminal to a source terminal of a first transistor related to the primary winding;
process information associated with the third voltage and a reference voltage; and
change a logic signal from a first logic level to a second logic level based at least in part on the second voltage and the reference voltage; and
a drive signal generator configured to:
receive the logic signal; and
in response to the logic signal changing from the first logic level to the second logic level,
change, at a first time, a first drive signal to turn off a second transistor related to the second auxiliary winding; and
change, at a second time, a second drive signal to turn on the first transistor related to the primary winding, the second time being after the first time by a predetermined delay.