US 12,323,060 B2
Buck-boost DC-DC converter circuit and corresponding method of operation
Nunzio Greco, Camporotondo Etneo (IT); Osvaldo Enrico Zambetti, Milan (IT); Ranieri Guerra, S. Giovanni la Punta (IT); and Francesca Giacoma Mignemi, S. Giovanni la Punta (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Apr. 10, 2023, as Appl. No. 18/297,998.
Claims priority of application No. 102022000008108 (IT), filed on Apr. 22, 2022.
Prior Publication US 2023/0344350 A1, Oct. 26, 2023
Int. Cl. H02M 3/157 (2006.01); H02M 1/00 (2006.01); H02M 3/158 (2006.01)
CPC H02M 3/1582 (2013.01) [H02M 1/0016 (2021.05); H02M 3/157 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A buck-boost DC-DC converter circuit, comprising:
a switching stage configured to receive a converter input voltage, a buck pulse-width modulated control signal and a boost pulse-width modulated control signal, and to produce a converter output voltage based on the buck pulse-width modulated control signal and the boost pulse-width modulated control signal;
an error amplifier circuit configured to sense the converter output voltage and a reference voltage, and produce an error signal indicative of a difference between the reference voltage and the converter output voltage;
an operation mode selection circuit configured to:
compare the converter input voltage to a lower threshold and an upper threshold,
assert a buck mode enable signal in response to the converter input voltage being higher than the lower threshold, and de-assert the buck mode enable signal in response to the converter input voltage being lower than the lower threshold, and
assert a boost mode enable signal in response to the converter input voltage being lower than the upper threshold, and de-assert the boost mode enable signal in response to the converter input voltage being higher than the upper threshold; and
a voltage shifter circuit configured to produce a buck control signal and a boost control signal based on the error signal, the buck mode enable signal and the boost mode enable signal, wherein the voltage shifter circuit is configured to:
in response to the buck mode enable signal being asserted and the boost mode enable signal being de-asserted, set VC,buck=VEA, where VC,buck is a value of the buck control signal and VEA is a value of the error signal;
in response to the buck mode enable signal being de-asserted and the boost mode enable signal being asserted, set VC,boost=(VEA−VFF), where VC,boost is a value of the boost control signal, and VFF is a value of a feedforward voltage of the buck-boost DC-DC converter circuit; and
in response to the buck mode enable signal being asserted and the boost mode enable signal being asserted, set VC,buck=(VEA−k2·Vref1) and VC,boost=(VEA−(k1+k2)·Vref1), where Vref1 is a value of the reference voltage, and k1 and k2 are values that satisfy the conditions k1+2·k2=1 and 0<k1<1.