US 12,322,743 B1
Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,093.
Application 17/552,093 is a continuation of application No. 17/550,910, filed on Dec. 14, 2021, granted, now 11,664,370.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/06 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 23/5286 (2013.01); H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, and wherein the via couples to a first metal layer;
a first capacitor including a first paraelectric dielectric material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;
a second capacitor including a second paraelectric dielectric material, wherein the electrode passes through a middle of the second capacitor;
a first input line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first input line is on an outer portion of the first capacitor;
a second input line extending along the x-plane or the z-plane, wherein the second input line is on an output portion of the second capacitor; and
a first transistor coupled to the via and a supply rail.