US 12,322,727 B2
Device and method for UBM/RDL routing
Meng-Tsan Lee, Hsinchu (TW); Wei-Cheng Wu, Hsinchu (TW); and Tsung-Shu Lin, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 6, 2019, as Appl. No. 16/562,990.
Application 16/562,990 is a division of application No. 15/157,312, filed on May 17, 2016.
Prior Publication US 2019/0393195 A1, Dec. 26, 2019
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/13609 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13616 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/13664 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73257 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/10252 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/10331 (2013.01); H01L 2924/10332 (2013.01); H01L 2924/10333 (2013.01); H01L 2924/10335 (2013.01); H01L 2924/10336 (2013.01); H01L 2924/10337 (2013.01); H01L 2924/10338 (2013.01); H01L 2924/10339 (2013.01); H01L 2924/10342 (2013.01); H01L 2924/10351 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first semiconductor die encapsulated within an encapsulant;
a through via extending from a first side of the encapsulant to a second side of the encapsulant;
a first redistribution layer electrically connected to the first semiconductor die, wherein the first redistribution layer comprises a first conductive feature and a second conductive feature;
a first dielectric layer over the first redistribution layer;
a second redistribution layer comprising:
a first conductive structure at least extending partially through the first dielectric layer and in physical contact with the first conductive feature of the first redistribution layer at a first interface, wherein the first interface is level with a surface of the first redistribution layer facing away from the through via and has a first width in a cross-sectional view; and
a second conductive structure at least extending partially through the first dielectric layer and in physical contact with the first conductive feature of the first redistribution layer at a second interface, wherein at least a part of the second interface is located directly over the through via, wherein the second interface is level with the surface of the first redistribution layer facing away from the through via and has a second width less than the first width in the cross-sectional view, wherein the first conductive feature of the first redistribution layer extends continuously beyond a side of the first interface opposite to the second interface and beyond a side of the second interface opposite to the first interface, wherein the second conductive structure of the second redistribution layer also extends continuously to be in physical contact with the second conductive feature of the first redistribution layer, the second conductive feature of the first redistribution layer being separated from the first conductive feature of the first redistribution layer by the first dielectric layer, a first portion of the first dielectric layer filling an entire area defined below the second conductive structure of the second redistribution layer to a straight line extending between a bottommost surface of the first conductive feature of the first redistribution layer and a bottommost surface of the second conductive feature of the first redistribution layer, the entire area being filled with only the first portion of the first dielectric layer;
an external connection in physical contact with the first conductive structure of the second redistribution layer; and
a second dielectric layer extending continuously from an interface with the external connection to completely cover a surface of the second conductive structure of the second redistribution layer facing away from the through via.