US 12,322,726 B2
Method of forming an integrated circuit package having a padding layer on a carrier
Cheng-Hsien Hsieh, Kaohsiung (TW); Li-Han Hsu, Hsin-Chu (TW); Wei-Cheng Wu, Hsinchu (TW); Der-Chyang Yeh, Hsin-Chu (TW); and Wei-Chih Lai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 1, 2022, as Appl. No. 17/683,377.
Prior Publication US 2023/0282614 A1, Sep. 7, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/1613 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32195 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit package, comprising:
forming a padding layer on a portion of a carrier;
placing a first semiconductor die on the padding layer and placing a second semiconductor die on the carrier;
encapsulating the first semiconductor die and the second semiconductor die with a first encapsulation layer;
forming a first redistribution layer structure over the first semiconductor die, the second semiconductor die and the first encapsulation layer;
placing a third semiconductor die on the first redistribution layer structure;
encapsulating the third semiconductor die with a second encapsulation layer;
forming a second redistribution layer structure over the third semiconductor die and the second encapsulation layer;
debonding the carrier; and
removing the padding layer and therefore forming a recess in the first encapsulation layer.