US 12,322,723 B2
Self-aligned interconnect structure
Hsin-Chieh Yao, Hsinchu (TW); Chung-Ju Lee, Hsinchu (TW); Chih Wei Lu, Hsinchu (TW); Hsi-Wen Tien, Xinfeng Township (TW); Yu-Teng Dai, New Taipei (TW); and Wei-Hao Liao, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,012.
Application 17/868,946 is a division of application No. 16/898,670, filed on Jun. 11, 2020, granted, now 11,488,926, issued on Nov. 1, 2022.
Application 18/359,012 is a continuation of application No. 17/868,946, filed on Jul. 20, 2022, granted, now 11,798,910.
Prior Publication US 2023/0369281 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 24/48 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76808 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, the method comprising:
forming a first conductive line between sidewalls of a first dielectric layer and over a semiconductor substrate;
depositing a second dielectric layer over the first dielectric layer and the first conductive line;
forming a first opening and a second opening in the second dielectric layer and on opposite sides of the first conductive line;
forming a first protective dielectric structure and a second protective dielectric structure in the first opening and the second opening, respectively;
forming a third opening in the second dielectric layer, over the first conductive line, and between the first protective dielectric structure and the second protective dielectric structure; and
forming a first conductive via in the third opening, the first conductive via coupled to the first conductive line.