	US 12,322,717 B2
	Semiconductor device and method for manufacturing a semiconductor device
Jens Hofrichter, Premstaetten (AT); Manuel Kaschowitz, Premstaetten (AT); Bernhard Poelzl, Premstaetten (AT); Karl Rohracher, Premstaetten (AT); Amandine Jouve, Premstaetten (AT); Viorel Balan, Premstaetten (AT); Romain Crochemore, Premstaetten (AT); Frank Fournel, Premstaetten (AT); and Sylvain Maitrejean, Premstaetten (AT)
Assigned to AMS AG, Premstaetten (AT); and COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, Paris (FR)
Appl. No. 17/607,194
Filed by ams AG, Premstaetten (AT); and Commissariat à l'énergie atomique et aux énergies alternatives, Paris (FR)
PCT Filed Mar. 30, 2020, PCT No. PCT/EP2020/058973 § 371(c)(1), (2) Date Oct. 28, 2021, PCT Pub. No. WO2020/221532, PCT Pub. Date Nov. 5, 2020.
Claims priority of application No. 19172269 (EP), filed on May 2, 2019.
Prior Publication US 2022/0223554 A1, Jul. 14, 2022
Int. Cl. H01L 23/48 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 21/00 (2006.01); H01L 23/00 (2006.01)

CPC H01L 24/08 (2013.01) [B81B 7/0006 (2013.01); B81C 1/00238 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); B81B 2207/017 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/03901 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1461 (2013.01)]

17 Claims

1. A semiconductor device comprising:

a substrate body with a surface;

a conductor comprising a conductor material covering at least part of the surface; and

a dielectric arranged on a part of the surface that is not covered by the conductor; wherein

the conductor is in contact with the substrate body;

the conductor and the dielectric form a layer;

a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body;

the semiconductor device is free of a diffusion barrier; and

the conductor comprises a sacrificial material, which is arranged on a surface of the conductor material facing away from the substrate body and comprises a conductive material that is different from the conductor material, wherein a thickness of the sacrificial material is less than or equal to a thickness of the conductor material,

wherein the dielectric and the sacrificial material form the bonding surface that is planarized to the surface topographies.

17. A method of manufacturing a semiconductor device comprising:

providing a substrate body with a surface;

depositing a conductor on the surface;

patterning and structuring the conductor;

depositing a dielectric on the conductor and on exposed parts of the surface; and

creating a bonding surface of the semiconductor device by removing part of the dielectric using a plurality of chemical-mechanical planarization (CMP) steps;

wherein the bonding surface has surface topographies of less than 10 nm;

wherein depositing the conductor comprises depositing a conductor material on the surface and depositing a sacrificial material on the conductor material, the sacrificial material being a conductive material that differs from the conductor material; and

creating the bonding surface comprises removing at least part of the sacrificial material,

wherein a layer of the sacrificial material is left on the semiconductor device, and

wherein the dielectric and the layer of the sacrificial material form the bonding surface that is planarized to the surface topographies.