US 12,322,714 B2
Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits
James Buckwalter, Santa Barbara, CA (US); Michael Hodge, Huntersville, NC (US); Justin Kim, San Jose, CA (US); Florian Herrault, Agoura Hills, CA (US); and Daniel Green, McLean, VA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Oct. 20, 2023, as Appl. No. 18/491,661.
Application 18/491,661 is a continuation of application No. 18/182,314, filed on Mar. 10, 2023, granted, now 11,810,876.
Prior Publication US 2024/0413103 A1, Dec. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/66 (2006.01); H03H 7/38 (2006.01)
CPC H01L 23/66 (2013.01) [H03H 7/38 (2013.01); H01L 2223/6605 (2013.01); H01L 2223/6661 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic assembly for heterogeneous integration of radio frequencies (RF) transistor chiplets having interconnections to or between tuning circuits, the assembly comprising:
a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks;
at least one chiplet having a second circuit including at least one RF transistor or RF switch device and passive tuning circuits for each of the at least one RF transistor or RF switch device, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network; and
electrical interconnects between the chiplets and the wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit, wherein:
the stabilization network includes: a) a first resistor between a first input of the first transistors device and a biasing node, a second resistor between a second input of the second transistors device and the biasing node, wherein the node is to a first AC ground and DC voltage that provides a first DC bias to the first and second inputs; and b) a resistor between the node and a second AC ground and DC voltage that provides a second DC bias to the first and second inputs.