US 12,322,713 B2
Transient stabilized SOI FETs
Robert Mark Englekirk, Littleton, CO (US); Keith Bargroff, San Diego, CA (US); Christopher C. Murphy, Lake Zurich, IL (US); Tero Tapio Ranta, San Diego, CA (US); and Simon Edward Willard, Irvine, CA (US)
Assigned to PSEMI CORPORATION, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Mar. 22, 2024, as Appl. No. 18/614,372.
Application 16/875,615 is a division of application No. 15/600,579, filed on May 19, 2017, granted, now 10,672,726, issued on Jun. 2, 2020.
Application 18/614,372 is a continuation of application No. 17/669,812, filed on Feb. 11, 2022, granted, now 11,948,897.
Application 17/669,812 is a continuation of application No. 16/875,615, filed on May 15, 2020, granted, now 11,251,140, issued on Feb. 15, 2022.
Prior Publication US 2024/0347482 A1, Oct. 17, 2024
Int. Cl. H01L 23/60 (2006.01); H01L 21/762 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H03K 17/0412 (2006.01); H03K 17/0416 (2006.01); H03K 17/042 (2006.01); H03K 17/14 (2006.01); H03K 17/687 (2006.01); H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 86/00 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)
CPC H01L 23/60 (2013.01) [H01L 21/76264 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H03K 17/04123 (2013.01); H03K 17/04163 (2013.01); H03K 17/04206 (2013.01); H03K 17/145 (2013.01); H03K 17/6872 (2013.01); H10D 30/6711 (2025.01); H10D 30/6713 (2025.01); H10D 30/6758 (2025.01); H10D 62/393 (2025.01); H10D 86/201 (2025.01); H10D 86/411 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for eliminating or reducing changes in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate including a trap rich layer susceptible to accumulated charge in or near such trap rich layer, the method including:
(a) providing a P-type field effect transistor (PFET) having a drain, a source, a gate, a VGS characteristic, and a signal path through the PFET between the drain and the source;
(b) coupling a first terminal of a controlled through-path switch to the drain of the PFET and a second terminal of the controlled through-path switch to a load, and configuring the controlled through-path switch to selectively couple the signal path of the PFET to the load when the controlled through-path switch is in a closed state or interrupt current flow through the signal path of the PFET when the controlled through-path switch is in an open state;
(c) coupling the source of the PFET to a supply voltage VDD;
(d) in an active mode, setting the controlled through-path switch to couple the signal path of the PFET to the load; and
(e) in a standby mode, setting the controlled through-path switch to interrupt current flow through the signal path of the PFET, thereby maintaining essentially the same VGS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge.