US 12,322,712 B2
Split source drain transistor
Joshua Joseph Trujillo, Overland Park, KS (US); and Payman Zarkesh-Ha, Albuquerque, NM (US)
Assigned to Honeywell Federal Manufacturing & Technologies, LLC, Kansas City, MO (US)
Filed by Honeywell Federal Manufacturing & Technologies, LLC, Kansas City, MO (US)
Filed on Dec. 12, 2023, as Appl. No. 18/537,236.
Application 18/537,236 is a continuation of application No. 18/150,942, filed on Jan. 6, 2023, granted, now 11,876,057.
Prior Publication US 2024/0234344 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 10/00 (2023.01); H01L 23/00 (2006.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H03K 3/03 (2006.01)
CPC H01L 23/576 (2013.01) [H10D 30/60 (2025.01); H10D 62/149 (2025.01); H03K 3/0315 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A transistor assembly comprising:
a split source and drain configuration comprising:
a source region including at least one source surface inflection segment disposed on an inner surface of the source region and protruding into a channel of the transistor assembly; and
a drain region separated from the source region by the channel, the drain region including at least one drain surface inflection segment disposed on an inner surface of the drain region and protruding into the channel,
wherein the at least one drain surface inflection segment is offset from the at least one source surface inflection segment along a length of the channel, and
wherein the at least one source surface inflection segment and the at least one drain surface inflection segment are configured to increase corner effects to thereby increase a variability of the transistor assembly.