US 12,322,705 B2
Chip package and manufacturing method thereof
Chuei-Tang Wang, Taichung (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 20, 2023, as Appl. No. 18/303,595.
Application 18/303,595 is a continuation of application No. 16/892,271, filed on Jun. 3, 2020, granted, now 11,676,906.
Application 16/892,271 is a continuation of application No. 15/905,722, filed on Feb. 26, 2018, granted, now 10,679,947, issued on Jun. 9, 2020.
Claims priority of provisional application 62/589,533, filed on Nov. 21, 2017.
Prior Publication US 2023/0260920 A1, Aug. 17, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/18 (2013.01); H01L 2224/214 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83191 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package, comprising:
an integrated circuit component, comprising:
a plurality of first semiconductor dies, each comprising a first active surface; and
a first insulating encapsulation, encapsulating the plurality of first semiconductor dies, wherein sidewalls of the plurality of first semiconductor dies are covered by the first insulating encapsulation;
a second semiconductor die, comprising a second active surface and a second rear surface opposite to the second active surface, and arranged next to the integrated circuit component in a horizontal direction; and
a second insulating encapsulation, encapsulating the integrated circuit component and the second semiconductor die, wherein sidewalls of the first insulating encapsulation and the second semiconductor die are covered by the second insulating encapsulation,
wherein a first surface of the second insulating encapsulation is substantially coplanar to the second active surface of the second semiconductor die.