US 12,322,703 B2
Eccentric via structures for stress reduction
Shu-Shen Yeh, Taoyuan (TW); Che-Chia Yang, Taipei (TW); Chia-Kuei Hsu, Hsinchu (TW); Po-Yao Lin, Zhudong Township (TW); Shin-Puu Jeng, Hsinchu (TW); and Chia-Hsiang Lin, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 9, 2024, as Appl. No. 18/766,974.
Application 18/766,974 is a continuation of application No. 17/126,881, filed on Dec. 18, 2020, granted, now 12,094,828.
Claims priority of provisional application 63/053,317, filed on Jul. 17, 2020.
Prior Publication US 2024/0363543 A1, Oct. 31, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a first dielectric layer;
a first via in the first dielectric layer;
a conductive feature over the first dielectric layer, wherein the conductive feature is over and joined to the first via;
a second dielectric layer covering and contacting the conductive feature;
a second via in the second dielectric layer;
a conductive pad over and contacting the second via;
a conductive bump over and contacting the conductive pad, wherein centers of the conductive pad and the conductive bump are vertically aligned to a vertical center line, wherein the vertical center line is perpendicular to an interface between the conductive pad and the conductive bump, and wherein an entirety of the first via is on an opposite side of the vertical center line than an entirety of the second via; and
an underfill, wherein the conductive bump and the conductive pad are in the underfill.