| CPC H01L 23/5283 (2013.01) [G06F 30/39 (2020.01); G06F 30/398 (2020.01); H01L 23/5226 (2013.01); H10D 64/661 (2025.01); H01L 2924/0002 (2013.01)] | 20 Claims |

|
1. An integrated chip, comprising:
a first gate contact arranged over a substrate and having a first topmost surface;
a second gate contact arranged over the substrate and having a second topmost surface;
a first via arranged on the first topmost surface, wherein a bottommost surface of the first via physically contacts a first part of the first topmost surface along an interface that is a non-zero distance over the substrate, and wherein the first topmost surface continuously extends in a first direction from directly below the first via to a second part of the first topmost surface that is laterally outside of the first via; and
a second via arranged on the second topmost surface, wherein a bottommost surface of the second via physically contacts a first part of the second topmost surface, and wherein the second topmost surface continuously extends in a second direction, which is opposite the first direction, from directly below the second via to a second part of the second topmost surface that is laterally outside of the second via.
|