US 12,322,696 B2
Dual-mode wireless charging device
Shih-Wei Liang, Dajia Township, Taichung County (TW); Hung-Yi Kuo, Taipei (TW); Hao-Yi Tsai, Hsinchu (TW); Ming-Hung Tseng, Toufen Township, Miaoli County (TW); and Hsien-Ming Tu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/232,312.
Application 16/671,644 is a division of application No. 15/222,815, filed on Jul. 28, 2016, granted, now 10,497,646.
Application 18/232,312 is a continuation of application No. 16/671,644, filed on Nov. 1, 2019, granted, now 11,735,518.
Prior Publication US 2023/0387003 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01F 27/28 (2006.01); H01F 17/00 (2006.01); H01F 41/04 (2006.01); H01F 41/061 (2016.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H02J 50/12 (2016.01); H10D 1/20 (2025.01); H10D 1/68 (2025.01); H01F 41/12 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/5227 (2013.01) [H01F 17/0013 (2013.01); H01F 27/2804 (2013.01); H01F 41/04 (2013.01); H01F 41/061 (2016.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/66 (2013.01); H02J 50/12 (2016.02); H10D 1/20 (2025.01); H10D 1/68 (2025.01); H01F 2017/0073 (2013.01); H01F 2027/2809 (2013.01); H01F 41/122 (2013.01); H01L 23/5389 (2013.01); H01L 24/20 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first molding layer formed on a substrate;
a first plurality of vias formed in the first molding layer;
a first conductive line formed over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias;
a second molding layer formed above the first molding layer;
a second plurality of vias formed in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the first conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another, wherein the second plurality of vias form a first conductive coil;
a third plurality of vias formed in the second molding layer, wherein the third plurality of vias form a second conductive coil interweaved with the first conductive coil; and
an integrated circuit die formed in the second molding layer and electrically coupling the integrated circuit die to the second conductive coil.