| CPC H01L 23/5223 (2013.01) [H10D 1/042 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01)] | 20 Claims |
|
1. A metal-insulator-metal (MIM) device, comprising:
a dielectric structure disposed over a semiconductor substrate;
a first metal plate disposed over the dielectric structure, the first metal plate having a first sidewall opposite a second sidewall;
a first capacitor insulator structure disposed over the first metal plate;
a second metal plate disposed over the first capacitor insulator structure, the second metal plate having a first sidewall opposite a second sidewall, wherein the first sidewall of the second metal plate is laterally offset from the first sidewall of the first metal plate, wherein the second sidewall of the second metal plate is aligned with the second sidewall of the first metal plate, and wherein the first capacitor insulator structure electrically insulates the first metal plate from the second metal plate;
a second capacitor insulator structure disposed over the second metal plate and the first capacitor insulator structure;
a third metal plate disposed over the second capacitor insulator structure, wherein the second capacitor insulator structure electrically insulates the second metal plate from the third metal plate;
a first conductive structure disposed over the dielectric structure and electrically coupled to both the first metal plate and the third metal plate; and
a second conductive structure disposed over the dielectric structure and laterally spaced from the first conductive structure, wherein the second conductive structure is electrically coupled to the second metal plate.
|
|
10. A metal-insulator-metal (MIM) device, comprising:
a first conductive layer disposed over a substrate;
a first capacitor dielectric disposed over the first conductive layer;
a second conductive layer disposed over the first capacitor dielectric, wherein the first conductive layer and the first capacitor dielectric laterally extend past an outermost sidewall of the second conductive layer;
a second capacitor dielectric disposed over the second conductive layer and the first capacitor dielectric;
a third conductive layer disposed over the second capacitor dielectric, wherein the third conductive layer laterally extends past the outermost sidewall of the second conductive layer and wherein the first conductive layer has a larger width than both the second conductive layer and the third conductive layer; and
a conductive structure coupled to both the first conductive layer and the third conductive layer, wherein the conductive structure vertically extends through the third conductive layer, the first capacitor dielectric, and the second capacitor dielectric to vertically contact an upper surface of the first conductive layer, and wherein the conductive structure extends through the first capacitor dielectric and the second capacitor dielectric laterally outside of the second conductive layer.
|
|
11. An integrated chip (IC), comprising:
a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate;
a metal-insulator-metal (MIM) device disposed on the first IMD structure, wherein the MIM device comprises:
at least three metal plates that are spaced from one another; and
a plurality of capacitor insulator structures, wherein each of the plurality of capacitor insulator structures are disposed between neighboring metal plates of the at least three metal plates;
wherein the at least three metal plates include a first metal plate, a second metal plate, and a third metal plate, the second metal plate laterally extending in a first direction past the third metal plate and the third metal plate laterally extending past the second metal plate in a second direction opposite the first direction; and
a dielectric material laterally surrounding the MIM device, wherein the dielectric material has a sidewall that laterally contacts outermost sidewalls of the first metal plate and the third metal plate and that is laterally separated from an outermost sidewall of the second metal plate by one of the plurality of capacitor insulator structures.
|