US 12,322,685 B2
Integrated circuit (IC) package with substrate having validation connectors
Luis Ricardo Perez-Corona, Tlaquepaque (MX); Maria Jose Garcia-Garcia de Leon, Zapopan (MX); Ricardo Astro-Bohorquez, Zapopan (MX); and Francisco Javier Ramirez-Aldana, Zapopan (MX)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 8, 2020, as Appl. No. 16/895,964.
Prior Publication US 2020/0303291 A1, Sep. 24, 2020
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 24/14 (2013.01); H01L 24/81 (2013.01); H01L 2224/1451 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
a package substrate;
a first set of one or more validation connectors on a first side of the package substrate, coupled with a set of one or more validation connectors of an IC die that is coupled with the first side of the package substrate, wherein the first set of one or more validation connectors is in an area between the IC die and the package substrate;
a second set of one or more validation connectors on the first side of the package substrate, coupled with the first set of one or more validation connectors, wherein the second set of one or more validation connectors is lateral of the IC die, outside of the area between the IC die and the package substrate; and
an interposer coupled to the second set of one or more validation connectors at a first side of the interposer, wherein the interposer includes, at a second side of the interposer opposite the first side of the interposer, one or more connectors configured to couple with a debug apparatus.