| CPC H01L 23/49811 (2013.01) [H01L 21/4853 (2013.01); H01L 23/13 (2013.01); H01L 23/49838 (2013.01)] | 14 Claims |

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1. A method, comprising:
providing a plurality of substrates having electrically-conductive tracks;
arranging a semiconductor chip on each substrate and electrically coupling the semiconductor chip to selected ones of said electrically-conductive tracks;
attaching said plurality of substrates onto a common base plate;
then providing containment structures at selected locations on said electrically-conductive tracks, wherein said containment structures have respective perimeter walls which define cavities having a size and shape configured to respectively accommodate a base portion of pin holders; and
soldering said pin holders within said cavities defined by said containment structures on said electrically-conductive tracks.
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