US 12,322,683 B2
Power module semiconductor device and inverter equipment, and fabrication method of the power module semiconductor device, and metallic mold
Toshio Hanada, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Mar. 29, 2024, as Appl. No. 18/622,153.
Application 18/622,153 is a continuation of application No. 18/491,223, filed on Oct. 20, 2023, granted, now 11,973,007.
Application 18/491,223 is a continuation of application No. 18/052,456, filed on Nov. 3, 2022, granted, now 11,967,543.
Application 18/052,456 is a continuation of application No. 17/119,243, filed on Dec. 11, 2020, granted, now 11,532,537.
Application 17/119,243 is a continuation of application No. 16/256,744, filed on Jan. 24, 2019, granted, now 10,896,866.
Application 16/256,744 is a continuation of application No. 15/903,665, filed on Feb. 23, 2018, abandoned.
Application 15/903,665 is a continuation of application No. 14/663,135, filed on Mar. 19, 2015, granted, now 9,960,103.
Application 14/663,135 is a continuation of application No. PCT/JP2013/074895, filed on Sep. 13, 2013.
Claims priority of application No. 2012-206947 (JP), filed on Sep. 20, 2012; and application No. 2012-207194 (JP), filed on Sep. 20, 2012.
Prior Publication US 2024/0282675 A1, Aug. 22, 2024
Int. Cl. H01L 23/482 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01); H01L 25/11 (2006.01); H01L 25/18 (2023.01); H02M 7/00 (2006.01)
CPC H01L 23/482 (2013.01) [H01L 21/50 (2013.01); H01L 21/565 (2013.01); H01L 23/3735 (2013.01); H01L 23/49811 (2013.01); H01L 23/49844 (2013.01); H01L 23/538 (2013.01); H01L 25/07 (2013.01); H01L 25/072 (2013.01); H01L 25/115 (2013.01); H01L 25/18 (2013.01); H02M 7/003 (2013.01); H01L 23/3107 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/207 (2013.01); H01L 2924/30107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power module semiconductor device comprising:
an insulating substrate having a first side, a second side adjacent to the first side, a third side opposite to the first side, and a fourth side opposite to the second side;
a first pattern disposed on a front surface of the insulating substrate;
first semiconductor chips disposed on the first pattern;
a negative side power input terminal electrically connected to the first semiconductor chips, the negative side power input terminal being disposed on the first side of the insulating substrate;
a first signal terminal electrically connected to the first semiconductor chips;
a second pattern disposed on the front surface of the insulating substrate;
second semiconductor chips disposed on the second pattern;
a positive side power input terminal electrically connected to the second semiconductor chips, the positive side power input terminal being disposed on the first side of the insulating substrate;
a second signal terminal electrically connected to the second semiconductor chips;
an output terminal electrically connected to the first semiconductor chips and the second semiconductor chips, the output terminal being arranged on the third side of the insulating substrate;
a third pattern disposed on a back surface of the insulating substrate; and
a resin layer having a main surface and a side surface and covering the first semiconductor chips, the second semiconductor chips, a part of the negative side power input terminal, a part of the positive side power input terminal, a part of the output terminal and the insulating substrate, wherein
the negative side power input terminal and the positive side power input terminal are disposed so as to be extended along in a parallel direction with the main surface of the resin layer,
the output terminal is disposed so as to be extended along in the parallel direction,
the third pattern is exposed from the resin layer, and
the third pattern is smaller than the insulating substrate as viewed in a thickness direction of the insulating substrate and is disposed inside a perimeter of the insulating substrate as viewed in a direction perpendicular to the thickness direction of the insulating substrate.