US 12,322,682 B2
Semiconductor package having composite seed-barrier layer and method of forming the same
Wei-Chung Chang, Taipei (TW); Ming-Che Ho, Tainan (TW); and Hung-Jui Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 5, 2023, as Appl. No. 18/482,006.
Application 18/482,006 is a continuation of application No. 17/458,610, filed on Aug. 27, 2021, granted, now 11,823,981.
Prior Publication US 2024/0047308 A1, Feb. 8, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/2855 (2013.01); H01L 21/76879 (2013.01); H01L 23/3157 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate, having a frontside surface and a backside surface opposite to each other, and a through hole connecting the frontside surface and the backside surface;
a conductive material, filled into the through hole to form a conductive via, wherein the conductive via has an upper surface within the backside surface of the substrate, so that the upper surface of the conductive via is recessed in the backside surface of the substrate;
a first composite seed-barrier layer, disposed on the backside surface of the substrate to cover the upper surface of the conductive via;
a second composite seed-barrier layer, extending between the conductive via and the first composite seed-barrier layer and further covering a sidewall of the conductive via, wherein an average thickness of the second composite seed-barrier layer covering the upper surface of the conductive via is substantially less than an average thickness of the second composite seed-barrier layer covering the sidewall of the conductive via; and
a conductive block, disposed on the first composite seed-barrier layer.