US 12,322,671 B2
Guard ring structure, semiconductor structure and manufacturing method
Hua Yan, Hefei (CN); and Hsin-Pin Huang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/605,733
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Jul. 8, 2021, PCT No. PCT/CN2021/105209
§ 371(c)(1), (2) Date Oct. 22, 2021,
PCT Pub. No. WO2022/188320, PCT Pub. Date Sep. 15, 2022.
Claims priority of application No. 202110270706.X (CN), filed on Mar. 12, 2021.
Prior Publication US 2024/0055309 A1, Feb. 15, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/304 (2006.01); H01L 21/78 (2006.01)
CPC H01L 23/3107 (2013.01) [H01L 21/304 (2013.01); H01L 21/78 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A guard ring structure, comprising:
a bottom metal layer; and
a protection structure located on the bottom metal layer, wherein the protection structure comprises, sequentially stacked from bottom to top, an insertion portion, an interconnection portion, and a metal layer, wherein the insertion portion is inserted into an underlying metal layer below the interconnection portion;
wherein a first gap is formed in the bottom metal layer, wherein the first gap penetrates the bottom metal layer to divide the bottom metal layer into a first bottom metal layers and a second bottom metal layer spaced apart; and
wherein the first gap is an annular gap, and wherein the first bottom metal layer, the second bottom metal layer, the insertion portion, the interconnection portion, and the metal layer in the protection structure are all ring structures around a protected chip.