US 12,322,658 B2
Dummy fin with reduced height and method forming same
Shih-Yao Lin, New Taipei (TW); Te-Yung Liu, Hsinchu (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 2, 2024, as Appl. No. 18/402,245.
Application 18/402,245 is a continuation of application No. 17/809,953, filed on Jun. 30, 2022, granted, now 11,894,274.
Application 17/809,953 is a continuation of application No. 16/942,076, filed on Jul. 29, 2020, granted, now 11,410,886, issued on Aug. 9, 2022.
Claims priority of provisional application 63/010,855, filed on Apr. 16, 2020.
Prior Publication US 2024/0186186 A1, Jun. 6, 2024
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/823418 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
isolation regions in the semiconductor substrate;
a protruding semiconductor fin higher than top surfaces of the isolation regions;
a gate stack on the protruding semiconductor fin;
a gate spacer on a sidewall of the gate stack, wherein the gate spacer contacts the sidewall of the gate stack to form a vertical interface;
a semiconductor region connecting to an end of the protruding semiconductor fin;
a contact etch stop layer over the semiconductor region;
an inter-layer dielectric over the contact etch stop layer; and
a dummy fin comprising:
a first portion directly underlying the gate stack and the gate spacer, wherein a sidewall of the first portion contacts a portion of the contact etch stop layer, and wherein the sidewall of the first portion of the dummy fin is in a vertical plane that is parallel to the vertical interface; and
a second portion overlapped by the contact etch stop layer.