US 12,322,657 B2
Wide band gap semiconductor process, device, and method
Tirunelveli Subramaniam Ravi, San Jose, CA (US); Hoeseok Lee, San Jose, CA (US); Bishnu Prasanna Gogoi, Scottsdale, AZ (US); and Jinho Seo, Saratoga, CA (US)
Assigned to ThinSiC Inc., Santa Clara, CA (US)
Filed by ThinSiC Inc., Santa Clara, CA (US)
Filed on Jul. 3, 2022, as Appl. No. 17/857,017.
Prior Publication US 2024/0006242 A1, Jan. 4, 2024
Int. Cl. H01L 21/78 (2006.01); H01L 21/02 (2006.01); H10D 8/01 (2025.01); H10D 8/60 (2025.01); H10D 62/832 (2025.01)
CPC H01L 21/7813 (2013.01) [H01L 21/02378 (2013.01); H01L 21/02532 (2013.01); H10D 8/051 (2025.01); H10D 8/60 (2025.01); H10D 62/8325 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor substrate for forming one or more semiconductor devices comprising:
a first silicon carbide epitaxial layer; and
a second silicon carbide epitaxial layer overlying the first silicon carbide epitaxial layer wherein the first silicon carbide epitaxial layer is grown overlying a surface of a silicon carbide substrate comprising silicon carbide and carbon, wherein the first silicon carbide epitaxial layer is configured to grow with a crystalline structure at the surface of the silicon carbide substrate, and wherein the first silicon carbide epitaxial layer is formed using merged epitaxial lateral overgrowth (MELO).