US 12,322,654 B2
Semiconductor structure, method for forming same, and wafer on wafer bonding method
Yuanhao Gao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 23, 2022, as Appl. No. 17/893,218.
Application 17/893,218 is a continuation of application No. PCT/CN2021/137465, filed on Dec. 13, 2021.
Claims priority of application No. 202111268970.6 (CN), filed on Oct. 29, 2021.
Prior Publication US 2023/0137875 A1, May 4, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 21/7684 (2013.01); H01L 23/481 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a wafer in which a semiconductor device is formed;
forming a blind hole in the wafer;
depositing a first metal material in the blind hole to form a through silicon via;
removing the first metal material deposited on a surface of the wafer, and planarizing the surface of the wafer; and
forming a bonding pad on a planarized surface of the wafer;
wherein the forming a bonding pad on a planarized surface of the wafer comprises:
depositing a hard mask layer on the planarized surface of the wafer;
patterning the hard mask layer to form a via exposing the metal interconnection layer and the blind hole; and
depositing a second metal material in the via to form the bonding pad.