US 12,322,653 B2
Self-aligned metal gate for multigate device and method of forming thereof
Jia-Chuan You, Taoyuan County (TW); Kuan-Ting Pan, Taipei (TW); Shi Ning Ju, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); and Chia-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/231,076.
Application 18/231,076 is a division of application No. 17/224,334, filed on Apr. 7, 2021, granted, now 11,961,763.
Claims priority of provisional application 62/705,716, filed on Jul. 13, 2020.
Prior Publication US 2024/0030066 A1, Jan. 25, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 21/76897 (2013.01) [H01L 21/02603 (2013.01); H01L 21/76805 (2013.01); H01L 21/76871 (2013.01); H01L 21/76895 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method including,
forming a first gate structure, a first source structure and a first drain structure of a first gate all around (GAA) device over a substrate;
forming a second gate structure, a second source structure and a second drain structure of a second GAA device over the substrate, wherein a dielectric fin is disposed between the first gate structure and the second gate structure;
depositing a dummy layer over the first gate structure, the second gate structure, and the dielectric fin;
patterning the dummy layer to form a trench within the dummy layer over the dielectric fin, the trench having a bottom surface of a first dielectric material of the dielectric fin, a first sidewall of the dummy layer and a second sidewall of the dummy layer, the second sidewall opposing the first sidewall;
filling the trench with a second dielectric material to form a dielectric feature extending from the first sidewall to the second sidewall and on the first dielectric material;
removing the patterned dummy layer after filling the trench and forming the dielectric feature; and
depositing at least one conductive layer having a first portion over the first gate structure and a second portion of the second gate structure, wherein the dielectric feature interposes the first portion and the second portion.