US 12,322,647 B2
Semiconductor devices and methods
Yu-Kai Lin, Changhua County (TW); Po-Cheng Shih, Hsinchu (TW); Jr-Hung Li, Chupei (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 3, 2022, as Appl. No. 17/831,884.
Claims priority of provisional application 63/268,182, filed on Feb. 17, 2022.
Prior Publication US 2023/0260832 A1, Aug. 17, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76829 (2013.01) [H01L 21/02178 (2013.01); H01L 21/02205 (2013.01); H01L 21/0228 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 23/53266 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a source/drain contact in electrical connection with a source/drain region over a semiconductor fin;
selectively depositing an etch stop layer on the source/drain contact;
depositing a dielectric layer over the etch stop layer, wherein after the depositing the dielectric layer the dielectric layer is in physical contact with a gate capping layer overlying a gate electrode;
forming a first conductive contact to the gate electrode through the gate capping layer; and
forming a second conductive contact to the source/drain contact through the etch stop layer.