US 12,322,569 B2
Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
Marcel Nicolaas Jacobus van Kervinck, Monster (NL); and Vincent Sylvester Kuiper, The Hague (NL)
Assigned to ASML Netherlands B.V., Veldhoven (NL)
Filed by ASML Netherlands B.V., Veldhoven (NL)
Filed on Oct. 4, 2021, as Appl. No. 17/493,816.
Application 17/493,816 is a continuation of application No. 16/331,538, granted, now 11,137,689, previously published as PCT/JP2017/033370, filed on Sep. 8, 2017.
Application 17/493,816 is a continuation of application No. 15/389,558, filed on Dec. 23, 2016, abandoned.
Claims priority of provisional application 62/458,040, filed on Feb. 13, 2017.
Claims priority of provisional application 62/385,049, filed on Sep. 8, 2016.
Prior Publication US 2022/0026815 A1, Jan. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01J 37/317 (2006.01); G03F 7/00 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); G06F 115/02 (2020.01); G06F 119/18 (2020.01)
CPC H01J 37/3177 (2013.01) [G03F 7/70383 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01J 37/3174 (2013.01); H01L 21/027 (2013.01); H01L 21/0274 (2013.01); H01L 21/0277 (2013.01); H01L 21/76816 (2013.01); H01L 23/573 (2013.01); G06F 2115/02 (2020.01); G06F 2119/18 (2020.01); H01J 2237/31764 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, which is a member of a set of semiconductor chips, comprising:
a common design layout part that is the same for all of the semiconductor chips of the set; and
a non-common design layout part that is the same for only a subset of the semiconductor chips of the set,
wherein the common design layout part and the non-common design layout part are formed in a plurality of layers, and
wherein the non-common design layout part includes at least one of: connections between a metal layer and a gate in a contact layer of the plurality of layers, or a P- or N-doped active region of a transistor of one of the plurality of layers.