US 12,322,474 B2
Memory device, read clock generation circuit, and method for controlling read operation in memory device
Sanjeev Kumar Jain, Kanata (CA); and Atul Katoch, Kanata (CA)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 7, 2023, as Appl. No. 18/297,094.
Prior Publication US 2024/0339140 A1, Oct. 10, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/08 (2013.01); G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array, comprising a plurality of memory cells in a two-dimensional array;
a read-clock generation circuit, configured to receive a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal;
a local input/output circuit, comprising:
a plurality of pairs of column-address pass gates, configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal; and
a pair of read pass gates, configured to connect a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state;
wherein the first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.