US 12,322,472 B2
Voltage generation circuit for SRAM
Hubert Martin Bode, Haar (DE); Alexander Hoefler, Austin, TX (US); and Glenn Charles Abeln, Buda, TX (US)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Aug. 22, 2022, as Appl. No. 17/821,260.
Prior Publication US 2024/0062791 A1, Feb. 22, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 5/14 (2006.01); G11C 7/14 (2006.01); H03K 19/094 (2006.01)
CPC G11C 7/1087 (2013.01) [G11C 5/14 (2013.01); G11C 7/14 (2013.01); H03K 19/09421 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory comprising:
a plurality of SRAM memory cells, each SRAM memory cell of the plurality of SRAM memory cells including an SRAM latch for storing a value;
a voltage generation circuit comprising:
a first reference generation circuit including a first group of at least one SRAM cell, each SRAM cell of the first group includes an SRAM latch that is a replica SRAM latch to SRAM latches of the plurality of SRAM memory cells, the first reference generation circuit providing a first voltage during an at least one mode of memory operation;
a second reference generation circuit including a second group of at least one SRAM cell, each SRAM cell of the second group includes an SRAM latch that is a replica SRAM latch to SRAM latches of the plurality of SRAM memory cells, the second reference generation circuit providing a second voltage during the at least one mode of memory operation;
a comparison circuit including a first input to receive the first voltage, a second input to receive the second voltage, and an output to provide an indication of the first voltage or the second voltage based on a comparison between the first voltage and the second voltage;
an output providing a supply voltage to the plurality of SRAM memory cells during the at least one mode of memory operation, a voltage level of the supply voltage being based on the output of the comparison circuit.