| CPC G11C 7/1069 (2013.01) [G11C 7/1063 (2013.01); G11C 7/1066 (2013.01); G11C 7/18 (2013.01)] | 20 Claims |
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1. A circuit comprising:
a plurality of memory banks;
a global bitline distributed to memory cells in each of the memory banks, the memory cells configured to utilize supply voltages from both of a write domain supply and a read domain supply;
the memory cells configured to output a stored value to the global bitline in response to a global read evaluation signal;
logic to maintain the global read evaluation signal in a timing window by adaptive adjustment of a delay for activating a keeper signal for the global read evaluation signal, the adaptive adjustment based on variations to at least one of the supply voltages;
a clock line configured to activate the keeper signal; and
the clock line comprising at least one delay element configured to have a propagation delay that tracks the variations.
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