| CPC G11C 7/1048 (2013.01) [G11C 7/222 (2013.01); G11C 2207/2254 (2013.01)] | 21 Claims |
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1. A semiconductor system comprising:
a controller configured to output a command address, a first chip selection signal, and a second chip selection signal; and
a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate a termination resistance value of the first rank based on the command address and the first chip selection signal and to calibrate a termination resistance value of the second rank based on the command address and the second chip selection signal;
wherein the first rank calibrates the termination resistance value of the first rank to a first resistance value based on the command address and the first chip selection signal when a write operation is performed on the first rank;
wherein the first rank calibrates the termination resistance value of the first rank to a second resistance value based on the second chip selection signal when a write operation is performed on the second rank;
wherein the first resistance value is different from the second resistance value; and
wherein a termination resistance value corresponds to a value that impedance matches a receiving end for data during the write operation.
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