US 12,322,469 B2
Managing page buffer circuits in memory devices
Ji-Yu Hung, Toufen (TW); and E-Yuan Chang, Chiayi (TW)
Assigned to Macronix International Co., Ltd., Hsinchu (TW)
Filed by Macronix International Co., Ltd., Hsinchu (TW)
Filed on Jan. 5, 2023, as Appl. No. 18/150,584.
Prior Publication US 2024/0233783 A1, Jul. 11, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1084 (2013.01); G11C 7/1087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array comprising memory cells;
a page buffer circuit comprising a plurality of page buffers coupled to the memory cell array; and
a cache data latch (CDL) circuit comprising a plurality of caches coupled to the plurality of page buffers in the page buffer circuit through a plurality of data bus (DBUS) sections,
wherein the plurality of DBUS sections are configured to be conductively connected together as a data bus for data transfer, and
wherein each DBUS section of the plurality of DBUS sections corresponds to a page buffer of the plurality of page buffers and is configured to conductively separate from at least one adjacent DBUS section for data sensing in the memory cell array.