US 12,322,466 B2
Memory device with redundancy for page-based repair
Alan John Wilson, Boise, ID (US); Donald M. Morgan, Meridian, ID (US); and John David Porter, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 2, 2024, as Appl. No. 18/761,619.
Application 18/761,619 is a continuation of application No. 17/823,740, filed on Aug. 31, 2022, granted, now 12,062,407.
Prior Publication US 2024/0363192 A1, Oct. 31, 2024
Int. Cl. G11C 29/54 (2006.01); G11C 29/00 (2006.01)
CPC G11C 29/76 (2013.01) [G11C 29/54 (2013.01); G11C 29/808 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a volatile memory;
a memory array comprising:
a plurality of prime rows; and
a set of redundant rows;
a memory controller configured to:
receive a first activate command comprising first defective address data for the memory array;
store the first defective address data in the volatile memory in association with a first soft post-package repair (SPPR) page of a redundant row of the set of redundant rows;
receive a second activate command comprising second defective address data for the memory device; and
store the second defective address data in the volatile memory in association with a second SPPR page of the redundant row of the memory device.