US 12,322,465 B2
Digital verify failbit count (VFC) circuit
Teng Chen, Wuhan (CN); and Masao Kuriyama, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Jan. 4, 2023, as Appl. No. 18/149,842.
Claims priority of application No. 202211677051.9 (CN), filed on Dec. 26, 2022.
Prior Publication US 2024/0212780 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/44 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/44 (2013.01) [G11C 29/1201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including one or more memory sections each including one or more memory cells;
a buffer circuit including one or more buffers each coupled to one of the one or more memory sections;
a verify failbit count (VFC) circuit coupled to the buffer circuit and including a counter, the counter including one or more counter stages coupled in series from an input of the counter; and
a control logic coupled to the VFC circuit and configured to control the counter to:
sequentially receive, at the input of the counter, a bit group including one or more verification bits, each of the one or more verification bits indicating a verification result of one memory cell in the memory cell array and being a fail bit or a pass bit; and
for one verification bit of the one or more verification bits, perform a determination process according to a position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.