US 12,322,458 B2
Memory device and method of operating the same
June Young Choi, Icheon-si (KR); and Un Sang Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 5, 2024, as Appl. No. 18/596,412.
Application 18/596,412 is a continuation of application No. 17/575,393, filed on Jan. 13, 2022, granted, now 11,961,574.
Claims priority of application No. 10-2021-0106153 (KR), filed on Aug. 11, 2021.
Prior Publication US 2024/0212769 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells to which a program voltage, which is incremental through a plurality of program loops, is applied through a word line;
a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the plurality of memory cells with a verify voltage on each of a plurality of program levels, and configured to apply a blind voltage related to a first program level among the plurality of program levels to the word line, the peripheral circuit comprising:
a plurality of page buffers connected to the plurality of memory cells via bit-lines and configured to store data as a result of the applying the blind voltage related to the first program level; and
a current sensing circuit configured to compare a reference current with a current corresponding to a number of fail-bits corresponding to the first program level from the data in the plurality of page buffers and transmit information on the number of fail-bits corresponding to the first program level, and
a control logic circuit configured to determine a program loop starting a verify operation corresponding to second program level, which has a higher threshold voltage level than the first program level, among the plurality of program levels based on the information received from the current sensing circuit,
wherein the blind voltage related to the first program level is the verify voltage corresponding to the first program level.