US 12,322,457 B2
Nonvolatile memory devices, operating methods thereof and memory systems including the same
Sun-Il Shim, Seoul (KR); Jae-Hoon Jang, Seongnam-si (KR); Donghyuk Chae, Seoul (KR); Youngho Lim, Yongin-si (KR); Hansoo Kim, Suwon-si (KR); and Jaehun Jeong, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 2, 2023, as Appl. No. 18/310,843.
Application 18/310,843 is a division of application No. 17/542,183, filed on Dec. 3, 2021, granted, now 11,715,537.
Application 17/542,183 is a division of application No. 17/342,048, filed on Jun. 8, 2021, abandoned.
Application 16/844,317 is a division of application No. 16/206,383, filed on Nov. 30, 2018, granted, now 10,650,903, issued on May 12, 2020.
Application 17/342,048 is a continuation of application No. 16/844,317, filed on Apr. 9, 2020, granted, now 11,062,784, issued on Jul. 13, 2021.
Application 16/206,383 is a continuation of application No. 15/664,303, filed on Jul. 31, 2017, granted, now 10,199,116, issued on Feb. 5, 2019.
Application 15/664,303 is a continuation of application No. 15/176,269, filed on Jun. 8, 2016, granted, now 9,747,995, issued on Aug. 29, 2017.
Application 15/176,269 is a continuation of application No. 14/849,029, filed on Sep. 9, 2015, granted, now 9,390,803, issued on Jul. 12, 2016.
Application 14/849,029 is a continuation of application No. 14/590,665, filed on Jan. 6, 2015, granted, now 9,330,770, issued on May 3, 2016.
Application 14/590,665 is a continuation of application No. 13/867,716, filed on Apr. 22, 2013, granted, now 8,964,476, issued on Feb. 24, 2015.
Application 13/867,716 is a continuation of application No. 12/986,798, filed on Jan. 7, 2011, granted, now 8,427,878, issued on Apr. 23, 2013.
Claims priority of provisional application 61/359,410, filed on Jun. 29, 2010.
Claims priority of application No. 10-2010-0014275 (KR), filed on Feb. 17, 2010.
Prior Publication US 2023/0268017 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/3459 (2013.01) [G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method of programming a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
programming each of the plurality of serially-connected nonvolatile memory cells by an incremental step pulse program (ISPP) method that uses a program voltage including an initial program voltage and an increment, a level of the program voltage increasing by the increment from a level of the initial program voltage; and
reading each of the plurality of serially-connected nonvolatile memory cells,
wherein the plurality of serially-connected nonvolatile memory cells are stacked on a substrate in a direction that is vertical to the substrate, and
the level of the initial program voltage of the program voltage that is applied to a corresponding one of the plurality of serially-connected nonvolatile memory cells is related with a distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate,
wherein the plurality of memory cell strings are on the substrate.