US 12,322,456 B2
Digital verify failbit count (VFC) circuit
Teng Chen, Wuhan (CN); and Masao Kuriyama, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Dec. 30, 2022, as Appl. No. 18/091,621.
Claims priority of application No. 202211677027.5 (CN), filed on Dec. 26, 2022.
Prior Publication US 2024/0212765 A1, Jun. 27, 2024
Int. Cl. G11C 29/44 (2006.01); G06F 16/2455 (2019.01); G11C 16/34 (2006.01); G11C 29/20 (2006.01); H03M 7/04 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/3459 (2013.01) [G06F 16/24554 (2019.01); G11C 29/20 (2013.01); G11C 29/44 (2013.01); H03M 7/04 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A verify failbit count (VFC) circuit comprising:
a counter circuit including a counter, the counter being configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format, the counter including:
a power-supply transistor, a first terminal of the power-supply transistor being configured to be coupled to a power supply; and
a plurality of counter stages each including:
a counter latch; and
a transistor string coupled between the counter latch and a second terminal of the power-supply transistor, the transistor string including a plurality of transistors coupled in series; and
a transcoder circuit including a transcoder coupled to the counter, the transcoder being configured to transcode the count result in unary format to a transcoded result in binary format.