US 12,322,455 B2
Program verify process having placement aware pre-program verify (PPV) bucket size modulation
Shantanu R. Rajwade, Santa Clara, CA (US); Tarek Ahmed Ameen Beshari, Santa Clara, CA (US); Matin Amani, Fremont, CA (US); Narayanan Ramanan, San Jose, CA (US); and Arun Thathachary, Santa Clara, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on May 14, 2021, as Appl. No. 17/321,114.
Prior Publication US 2022/0366991 A1, Nov. 17, 2022
Int. Cl. G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
controller logic circuitry to perform a program-verify programming process to a flash memory chip, wherein, the program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state, the number of cells being less than a total number of cells to be programmed to the same digital state,
wherein cells in the PPV bucket comprise cells having read voltage that is less than a first read verify voltage threshold (“VFY”) corresponding to the same digital state and above a second verification read voltage threshold (pre-verify (P-VFY)) that is less than VFY.