US 12,322,453 B2
NAND IO bandwidth increase
Tianyu Tang, Milpitas, CA (US); Venkatesh Prasad Ramachandra, San Jose, CA (US); and Siddhesh Darne, Milpitas, CA (US)
Assigned to SANDISK TECHNOLOGIES, INC., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Aug. 29, 2022, as Appl. No. 17/898,386.
Prior Publication US 2024/0071519 A1, Feb. 29, 2024
Int. Cl. G11C 16/26 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/26 (2013.01) [G06F 3/0635 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A NAND circuit comprising:
a controller configured to perform a write operation, wherein the controller includes a controller input/output (I/O) circuit; and
a NAND memory die comprising a memory die I/O circuit communicatively connected to the controller I/O circuit via a plurality of buses, wherein the plurality of buses comprise:
a bidirectional data strobe (DQS) bus configured to transmit a DQS data signal and an inverse data strobe (BDQS) data signal from the controller I/O circuit to the memory die I/O circuit during the write operation, wherein the DQS data signal represents a binary value and the BDQS data signal represents a binary value,
a read enable (RE) bus configured to transmit a clock signal between the controller I/O circuit and the memory die I/O circuit during the write operation, and
an I/O bus configured to transmit a data signal between the controller I/O circuit and the memory die I/O circuit during the write operation, wherein the data signal represents 8 binary values;
wherein the memory die I/O circuit comprises:
a first two input multiplexer communicatively connected to an input clock network, a first input receiver and a first dual tail sense amplifier, and
a second two input multiplexer communicatively connected to the input clock network, the first input receiver and a second dual tail sense amplifier.