US 12,322,452 B2
Three-dimensional memory device including a bit-line-bias vertical transistor block and methods of operating the same
Naoto Norizuki, Yokkaichi (JP); and Hiroki Yabe, Yokohama (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US)
Filed on Aug. 1, 2023, as Appl. No. 18/363,518.
Claims priority of provisional application 63/498,915, filed on Apr. 28, 2023.
Prior Publication US 2024/0363170 A1, Oct. 31, 2024
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 80/00 (2023.01)
CPC G11C 16/16 (2013.01) [G11C 16/0483 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of memory blocks, wherein each memory block within the plurality of memory blocks comprises a respective alternating stack of insulating layers and word lines and a respective two-dimensional array of NAND strings, wherein each of the NAND strings comprises a respective vertical stack of memory elements, a respective vertical semiconductor channel, and a respective drain region;
a bit-line-bias block located adjacent to the plurality of memory blocks and comprising an alternating stack of dummy insulating layers and dummy word lines and a two-dimensional array of dummy NAND strings, wherein each of the dummy NAND strings comprises a respective vertical stack of dummy memory elements, a respective dummy vertical semiconductor channel, and a respective dummy drain region;
bit lines each extending over the plurality of memory blocks and the bit-line-bias block and electrically connected to a respective drain region within each memory block within the plurality of memory blocks and to a respective dummy drain region;
a source line electrically connected to each end of the vertical semiconductor channels and the dummy vertical semiconductor channels located at an opposite side of the bit lines; and
an erase operation control circuit configured to apply a source-drain erase bias voltage between the source line and the bit lines through the dummy vertical semiconductor channels within the bit-line-bias block during an erase operation.