US 12,322,451 B2
Memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods
Pitamber Shukla, Boise, ID (US); Jiun-Horng Lai, Kanagawa (JP); Ching-Huang Lu, Fremont, CA (US); Fulvio Rori, Boise, ID (US); Wai Ying Lo, Boise, ID (US); and Scott A. Stoller, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 9, 2022, as Appl. No. 17/739,789.
Prior Publication US 2023/0360708 A1, Nov. 9, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/3445 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array, and
an internal processing circuit configured to:
receive an erase suspend command while a first erase pulse of an erase operation of memory cells of the memory array is at a flattop voltage;
in response to the erase suspend command, immediately suspend the erase operation, wherein a first total amount of time represents a duration that the first erase pulse remained at the flattop voltage before suspending the erase operation; and
resume the erase operation, wherein resuming the erase operation includes ramping a second erase pulse of the erase operation to the flattop voltage,
wherein the first erase pulse and the second erase pulse represent segments of a full erase pulse of erase operations of the memory device that, absent intervening erase suspend commands, remains at the flattop voltage for a total amount of time, and
wherein a sum of (a) the first total amount of time and (b) a second total amount of time the second erase pulse remains at the flattop voltage, is less than or equal to the total amount of time the full erase pulse remains at the flattop voltage.