US 12,322,450 B2
Memory programming using consecutive coarse-fine programming operations of threshold voltage distributions
Huai-Yuan Tseng, San Ramon, CA (US); Giovanni Maria Paolucci, Milan (IT); Kishore Kumar Muchherla, Fremont, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); and Akira Goda, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 24, 2023, as Appl. No. 18/138,551.
Claims priority of provisional application 63/339,902, filed on May 9, 2022.
Prior Publication US 2023/0360705 A1, Nov. 9, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01)
CPC G11C 16/12 (2013.01) [G11C 16/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising memory cells and wordlines; and
control logic operatively coupled with the memory array, the control logic to perform operations comprising:
causing a first set of memory cells, associated with a first wordline of the memory array, to be programmed with a first set of threshold voltage distributions;
causing a second set of memory cells, associated with a second wordline that is adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions;
after programming the second set of memory cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set of threshold voltage distributions; and
causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions, wherein at least some threshold voltage distributions of the final third set of threshold voltage distributions comprise wider read window margins than those of the intermediate third set of threshold voltage distributions.