US 12,322,448 B2
Memory device and operating method of the memory device
Hee Youl Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 26, 2023, as Appl. No. 18/101,954.
Claims priority of application No. 10-2022-0095395 (KR), filed on Aug. 1, 2022.
Prior Publication US 2024/0038306 A1, Feb. 1, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/14 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first select transistor, a plurality of memory cells, and a second select transistor, connected between a source line and a bit line; and
a peripheral circuit configured to perform a pre-program operation on the plurality of memory cells and then perform an erase operation on the plurality of memory cells,
wherein, in the pre-program operation, the peripheral circuit is configured to apply a program voltage to word lines that are connected to the plurality of memory cells corresponding to a channel that has been floated.