US 12,322,446 B2
Reduced word line voltage during discharge phase of read operation
Himanshu Saxena, Karnataka (IN)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 4, 2022, as Appl. No. 17/657,814.
Claims priority of application No. 202141058811 (IN), filed on Dec. 16, 2021.
Prior Publication US 2023/0197162 A1, Jun. 22, 2023
Int. Cl. G11C 17/16 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 17/12 (2006.01); G11C 17/18 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 17/12 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A One Time Programmable (OTP) memory comprising:
a plurality of bitcells;
a plurality of bitlines, each bitline coupled to the plurality of bitcells; and
a wordline generation circuit coupled to each of the plurality of bitcells, the word line generation circuit comprising a reference voltage circuit, a regulator, a level shifter, and a P-type metal-oxide-semiconductor (PMOS) driver coupled in series,
wherein the wordline generation circuit is configured to:
control a wordline voltage of at least one selected bitcell of the plurality of bitcells to discharge current of at least one bitline coupled to the at least one selected bitcell during a pre-conditioning phase and to perform a read operation of the at least one selected bitcell following the pre-conditioning phase in a same cycle of a bit line discharge pulse signal, and
wherein the reference voltage circuit is configured to:
change a reference voltage for the regulator during the pre-conditioning phase and the read operation following the pre-conditioning phase in the same cycle of the bit line discharge pulse signal; and
apply the changed reference voltage on the regulator,
wherein the regulator is configured to:
change a regulated output voltage based on the applied change reference voltage during the pre-conditioning phase and the read operation following the pre-conditioning phase in the same cycle of the bit line discharge pulse signal; and
provide the changed regulated output voltage to the PMOS driver through the level shifter;
wherein the PMOS driver is configured to:
control the wordline voltage of the at least one selected bitcell based on the received changed regulated output voltage from the regulator during the pre-conditioning phase and the read operation following the pre-conditioning phase in the same cycle of the bit line discharge pulse signal, wherein the controlled wordline voltage of the at least one selected bitcell controls the discharge current of the respectively coupled at least one bitline during the pre-conditioning phase that is followed by the read operation of the same cycle of the bit line discharge pulse signal.