US 12,322,445 B2
Three dimensional semiconductor memory structure
Kaiwei Cao, Hubei (CN); Peng Sun, Hubei (CN); Jun Zhou, Hubei (CN); Qiong Zhan, Hubei (CN); Wei Huang, Hubei (CN); and Chunyuan Hou, Hubei (CN)
Assigned to Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Hubei (CN)
Filed by Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Hubei (CN)
Filed on Nov. 10, 2022, as Appl. No. 17/985,064.
Application 17/985,064 is a continuation of application No. PCT/CN2020/107603, filed on Aug. 7, 2020.
Claims priority of application No. 202010529695.8 (CN), filed on Jun. 11, 2020.
Prior Publication US 2023/0073118 A1, Mar. 9, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/24 (2013.01); G11C 16/30 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a memory-array unit, comprising a substrate, a memory array disposed on the substrate, and a first bonding region disposed around the memory array, wherein:
the memory array comprises a plurality of word lines, a plurality of bit lines, and a plurality of source lines;
the first bonding region comprises a first substrate-connecting bonding region, a first bit-line bonding region, a first word-line bonding region, and a first source-line bonding region; and
the first substrate-connecting bonding region is configured to connect the substrate electrically to a surface of the memory-array unit, the first bit-line bonding region is configured to connect the plurality of bit lines electrically to the surface of the memory-array unit, the first word-line bonding region is configured to connect the plurality of word lines electrically to the surface of the memory-array unit, and the first source-line bonding region is configured to connect the plurality of source lines electrically to the surface of the memory-array unit,
wherein the memory array has NOR flash architecture.