US 12,322,444 B2
Memory devices with controlled wordline ramp rates, and associated systems and methods
Allahyar Vahidimowlavi, San Jose, CA (US); and Kalyan C. Kavalipurapu, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 23, 2021, as Appl. No. 17/238,482.
Application 17/238,482 is a continuation of application No. 16/752,981, filed on Jan. 27, 2020, granted, now 11,004,513.
Application 16/752,981 is a continuation of application No. 16/214,007, filed on Dec. 7, 2018, granted, now 10,546,641, issued on Jan. 28, 2020.
Prior Publication US 2021/0241832 A1, Aug. 5, 2021
Int. Cl. G11C 16/12 (2006.01); G11C 5/06 (2006.01); G11C 8/08 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 5/063 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 16/0416 (2013.01); G11C 16/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device configured to, for a single program pulse, (a) ramp a selected wordline to a desired programming voltage in more than two steps and (b) ramp an unselected wordline from ground to a desired inhibit voltage in more than two steps such that the unselected wordline reaches the desired inhibit voltage at a same time that the selected wordline reaches the desired programming voltage.