US 12,322,442 B2
Resistive memory with low voltage operation
Zheng-Jun Lin, Taichung (TW); Chung-Cheng Chou, Hsinchu (TW); and Yu-Der Chih, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 1, 2024, as Appl. No. 18/760,971.
Application 18/760,971 is a continuation of application No. 17/828,979, filed on May 31, 2022, granted, now 12,027,205.
Claims priority of provisional application 63/294,721, filed on Dec. 29, 2021.
Prior Publication US 2024/0355389 A1, Oct. 24, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0033 (2013.01); G11C 2213/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of Resistive Random Access Memory (RRAM) memory cells arranged in rows and columns;
wherein each RRAM memory cell of the array of RRAM memory cells comprises:
an access transistor, wherein a drain/source of the access transistor is connected to the source line, and
a RRAM resistive element, wherein a first terminal of the RRAM resistive element is connected to the bit line and a second terminal of the RRAM resistive element is connected to the source/drain of the access transistor; and
a metal wiring connected between the source and the drain of the access transistor.