US 12,322,440 B2
Programming operation of memory device being switched from high-density mode to high speed mode and/or lower power mode
Violante Moschiano, Avezzano (IT); and Andrea Smaniotto, Albignasego (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 1, 2022, as Appl. No. 17/901,430.
Application 16/418,016 is a division of application No. 15/456,175, filed on Mar. 10, 2017, abandoned.
Application 17/901,430 is a continuation of application No. 16/418,016, filed on May 21, 2019, granted, now 11,437,093.
Prior Publication US 2022/0415389 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/56 (2006.01); G06F 1/30 (2006.01); G11C 5/14 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01)
CPC G11C 11/5628 (2013.01) [G06F 1/30 (2013.01); G11C 5/143 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 2211/5641 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a non-volatile memory comprising a plurality of memory cells; and
a controller configured to:
begin a first programming operation configured to program a plurality of bits of information to a first one of the plurality of memory cells, wherein the first one of the plurality of memory cells has been previously programmed with one or more additional bits of information,
terminate the first programming operation in response to receiving a command from a connected host device to switch from a high-density operation mode to a high speed mode and/or a lower power mode and without reference to a current or impending power loss event, and
program, with a second programming operation, a second one of the plurality of memory cells with the plurality of bits of information.